s upertex inc. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 222-8888 fax: (408) 222-4895 www.supertex.com 1 nr040506 HV732 initial release high speed 100v 2a integrated ultrasound pulser features hvcmos technology for high performance 0 to 100v output voltage 2a source and sink current built-in damping for rtz waveform capability gate-clamp for quick output amplitude ramping up to 40mhz operation frequency 3ns matched delay times second harmonic is less than -40db 1.8v to 3.3v cmos logic interface 7x7 thermally-enhanced 44-lead qfn mcm application medical ultrasound imaging ? ? ? ? ? ? ? ? ? ? ? general description the supertex HV732 is a single, complete, high-voltage, high-speed, ultrasound transmitter pulser. it is designed for medical ultrasound imaging applications. the HV732 has built-in damping for faster rtz waveform capability and high voltage mosfet gate-clamping function for quick ramping of the output voltage amplitude. the HV732 consists of a control logic circuit, level translators, mosfet gate drive buffers, clamp circuits, and high current, high voltage mosfets as the ultrasound transmitter pulser output stage. in the output stage there are two pairs of mosfets. each pair consists of a p-channel and an n-channel mosfet. they are designed to have the same impedance, and can provide peak currents of over 2 amps. the built-in mosfet gate driver outputs swing 0 to 12v on p dr and n dr pins. the p-channel damp output swings 0 to C5v on the dmpo pin. typical application circuit level trans. damp level trans. +12v level trans. +12v v sub substrate, pad 1 +5 to 12v v dd agnd v ll v ln clamp en gnd +1.8 to 3.3v -5v on/off clamp circuit n in av dd bias p in p dr tx n v nn tx p v pp out n out p rgnd p dmpi n dr dmpo n gate p gate 10nf 0 to +100v 0 to -100v hv out pad 3 pad 2 0v rgnd n 10nf 10nf buffer buffer
2 nr040506 HV732 ordering information device package options 44-lead qfn HV732 HV732k6 HV732k6-g -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v ll , logic supply -0.5v to +5.5v v dd , positive gate drive supply -0.5v to +15v av dd , positive gate drive supply -0.5v to +15v v ln , negative gate drive supply -5.5v to +0.5v v pp -v nn , differential high voltage supply +220v v pp , high voltage positive supply -0.5v to +200v v nn , high voltage negative supply +0.5v to -200v storage temperature -65c to 150c thermal enhanced package power dissipation 1.5w symbol parameter min typ max units conditions operating supply voltages and current (over recommended operating conditions unless otherwise speci? ed: av dd = v dd = 12v, v ll = 3.3v, v ln = -5v, t a = 25c) absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. power-up sequence 1v pp and v sub 2v nn 3v ln 4v dd 5v ll v ll logic supply 1.8 3.3 3.6 v --- av dd positive analog supply 9.0 - 12.6 v --- v dd positive drive supply 9.0 - 12.6 v --- v pp high voltage positive supply for hv out p1 0 - 100 v --- v nn high voltage negative supply for hv out n1 -100 - 0 v --- v ln high voltage negative supply for hv out n2 -4.75 -5.0 -5.25 v --- v sub high voltage positive supply for to bias substrate --100v need to be the most positive supply on the device i ddq v dd current en = low - 175 290 a --- i dden v dd current en = high - 1.7 2.8 ma p in = n in = low i dden v dd current at 5mhz pw - 7.5 - ma f = 5.0mhz, pw d% = 1.0% no cap on p dr , n dr i ppq v dd current en = low - 2.0 5.0 a v pp = +100v, v nn = -100v i ppen v dd current en = high - 140 180 a p in = n in = low, v pp = +100v, v nn = -100v i nnq v dd current en = low - -1.0 -3.0 a v pp = +100v, v nn = -100v
3 nr040506 HV732 i nnen v dd current en = high - -140 -180 a p in = n in = low, v pp = +100v, v nn = -100v i llq v dd current en = low - 1.0 5.0 a --- i llen v dd current en = high - 16 25 a p in = n in = low i lnq v dd current en = low - -1.0 -5.0 a --- i lnen v dd current en = high - -230 -320 a p in = n in = low operating supply voltages and current (cont.) (over recommended operating conditions unless otherwise speci? ed: av dd = v dd = 12v, v ll = 3.3v, v ln = -5v, t a = 25c) symbol parameter min typ max units conditions dc electrical characteristics (over recommended operating conditions unless otherwise speci? ed: av dd = v dd = 12v, v ll = 3.3v, v ln = -5v, t a = 25c) symbol parameter min typ max units conditions output p-channel mosfet, tx p i out output saturation current -2.0 - - a v gs = -10v, v ds = -25v r on channel resistance - - 8 v gs = -10v, i ds = -1.0a r gs gate to source resistor 10 - 50 k i gs = -100a v gs source to gate zener voltage -13.2 - -25 v i gs = -2.0a v gsf gate zener forward voltage -0.5 - -0.8 v --- v gs(th) gate threshold voltage -1.0 - -2.4 v i ds = -1.0ma c iss input capacitance - - 200 pf v gs = 0v, v ds = -25v, f = 1mhz c oss output capacitance - 25 55 pf output n-channel mosfet, tx n i out output saturation current 2.0 - - a v gs = -10v, v ds = -25v r on channel resistance - 7.0 v gs = -10v, i ds = -1.0a r gs gate to source resistor 10 - 50 k i gs = -100a v gs source to gate zener voltage 13.2 - 25 v i gs = -2.0a v gsf gate zener forward voltage 0.5 - 0.8 v --- v gs(th) gate threshold voltage 1.0 - 2.0 v i ds = -1.0ma c iss input capacitance - - 110 pf v gs = 0v, v ds = -25v, f = 1mhz c oss output capacitance - 28 60 pf symbol parameter min typ max units conditions output p-channel damp mosfet, out p i out output saturation current - -1.0 - a v gs = -10v, v ds = -25v r on channel resistance - - 30 v gs = -10v, i ds = -1.0a r gs gate to source resistor - 75 100 k i gs = -100a v gs source to gate zener voltage -13.2 - -25 v i gs = -2.0a v gsf gate zener forward voltage 0.5 - 0.8 v --- v gs(th) gate threshold voltage -1.0 - -2.6 v i ds = -1.0ma c iss input capacitance - - 200 pf v gs = 0v, v ds = -25v, f = 1mhz c oss output capacitance - - 60 pf symbol parameter min typ max units conditions
4 nr040506 HV732 output n-channel damp mosfet, out n i out output saturation current 1.0 - - a v gs = 10v, v ds = 25v r on channel resistance - - 22 v gs = 10v, i ds = 0.5a v gs source to gate zener voltage 1.0 - 2.6 v i ds = 1.0a c iss input capacitance - - 110 pf v gs = 0v, v ds = 25v, f = 1mhz c oss output capacitance - - 60 pf symbol parameter min typ max units conditions p-channel gate driver output, p dr r sink output sink resistance - 10 15 i pdr = 100ma r source output source resistance - 8.0 13 i pdr = -100ma i pdr peak output sink current - 2.0 - a --- i pdr peak output source current - -2.0 - a --- symbol parameter min typ max units conditions n-channel gate driver output, n dr r sink output sink resistance - 8.0 13 i ndr = 100ma r source output source resistance - 9.0 14 i ndr = -100ma i ndr peak output sink current - 1.0 - a --- i ndr peak output source current - -1.0 - a --- symbol parameter min typ max units conditions p-channel gate driver output, dmpo r sink output sink resistance - 26 30 i dmpo = 100ma r source output source resistance - 15 30 i dmpo = -100ma i dmpo peak output sink current - 0.3 - a --- i dmpo peak output source current - -0.3 - a --- symbol parameter min typ max units conditions p-channel gate clamp mosfet i out output saturation current - 100 - a --- r on channel resistance - 60 80 --- c oss output capacitance - 40 - pf v gs = 0v, v ds = 25v, f = 1mhz symbol parameter min typ max units conditions n-channel gate clamp mosfet i out output saturation current - 50 - a --- r on channel resistance - 25 50 --- c oss output capacitance - 40 - pf v gs = 0v, v ds = 25v, f = 1mhz symbol parameter min typ max units conditions
5 nr040506 HV732 logic inputs t irf inputs rise and fall time - - 10 ns logic input edge speed requirement v ih input logic high voltage 0.8v ll -v ll v --- v il input logic low voltage 0 - 0.2v ll v --- i ih input logic high current - - 1.0 a --- i il input logic low current -1.0 - - a --- symbol parameter min typ max units conditions ac electrical characteristics (over recommended operating conditions unless otherwise speci? ed: av dd = v dd = 12v, v ll = 3.3v, v ln = -5v, t a = 25c) f out output frequency range - - 40 mhz see test curcuit and timing diagram tr output rise time - 10 - ns see relevant test circuit and timing diagram. load = 1.0k/220pf tf output fall time - 10 - ns tdr delay time on rise time - 12 - ns tdf delay time on fall time - 12 - ns t delay delay time matching - - 3.0 ns from device to device hd2 second harmonic distortion - -40 - db 100 resistor load t jitter output jitter - 80 - ps standard deviation of t d samples (1k) t en enable time - 30 50 s see timing diagram t dmpon(p) damp switch on delay (p) - 17 22 ns out p 50 to -15v, 10nf from dmpo to dmpi. see timing diagram. t dmpoff(p) damp switch off delay (p) - 20 26 ns t dmpon(n) damp switch on delay (n) - 13 17 ns out n 50 to +15v. see timing diagram. t dmpoff(n) damp switch off delay (n) - 13 17 ns t clpon(p) clamp switch on delay (p) - 430 1000 ns p gate 75 to 0v, 10nf to p dr , v pp = +12v. see timing diagram. t clpoff(p) clamp switch off delay (p) - 490 1000 ns t clpon(n) clamp switch on delay (n) - 330 550 ns n gate 75 to 0v, 10nf to n dr , v nn = -12v. see timing diagram. t clpoff(n) clamp switch off delay (n) - 316 500 ns t pwrup device power-up delay - 150 200 s all power supplies up and stable symbol parameter min typ max units conditions truth table logic control inputs gate drive output hv output damp output en p in n in clamp damp p dr n dr dmpo tx p tx n out p out n 1 0 0 0 0 h l h off off off off 1 1 000 l lh on off off off 10 1 00h h h off on off off 1 xx1 0 h l h off off off off 1000 1 hl l off off on on 0 x x x x h l h off off off off
6 nr040506 HV732 HV732 test circuit level trans. damp level trans. +12v buffer level trans. +12v buffer v sub +5 to 12v v dd agnd v ll v ln clamp en gnd +1.8 to 3.3v -5v on/off clamp circuit n in av dd bias p in p dr tx n v nn tx p v pp out n out p dmpi n dr dmpo n gate p gate 10nf 10nf 10nf hv out 0v r load 100 substrate, pad 1 pad 3 pad 2 rgnd p rgnd n HV732 tx switching time test 10nf 10nf 10nf 0 to +100v 0 to -100v hv out -5v +3.3v +12v to oscilloscope r l 1k 20mhz 3v 0-p 0 ? 10 ? +100v c l 220pf damp v sub v dd p in agnd v ll v ln clamp en gnd n in av dd p dr tx n v nn tx p v pp out n out p rgnd p dmpi n dr dmpo n gate p gate rgnd n HV732
7 nr040506 HV732 HV732 timing diagram en p in n in n dr p dr hv out damp 1us 1us clamp v pp 30us v pp v nn 0v i avdd 0.175ma 2ma 1.5ma 30us
8 nr040506 HV732 HV732 damp switching time diagram HV732 clamp switching time diagram t dmpon(n) 50% 10% 50% 90% damp damp out 0v t dmpoff(n) v nn t dmpon(p) 50% 10% 50% 90% t dmpoff(p) 0v v pp t clpon(p) 50% 10% 50% 90% clamp hv out 0v t clpoff(p) v nn t clpon(n) 50% 10% 50% 90% t clpoff(n) 0v v pp HV732 tx switching time diagram t dr 50% 10% 50% 90% p in n in t df hv out v nn v pp t r 10% 90% t f 90% 10%
9 nr040506 HV732 pin description pin function description 1 dmpo output of low voltage drive buffer for p-channel damp, 10nf external cap to pin 34 (dmpi) 2 gnd drive power ground 3n dr output of low voltage drive buffer for n-dmos, 10nf external cap to pin 9 (ngate) 4v dd positive voltage supply for drive circuitry (+12v) 5 vdd positive voltage supply for drive circuitry (+12v) 6v sub substrate connection of control / driver die chip (connected to the most positive supply, v pp ) 7 rgnd n ground return of damp n-dmos source 8 out n output of damp n-dmos drain (open drain output) 9 ngate gate input of the high voltage n-dmos, 10nf external cap from pin 3 (n dr ) 10 v nn negative high voltage power supply (-100v) 11 v nn negative high voltage power supply (-100v) 12 v nn negative high voltage power supply (-100v) 13 v nn negative high voltage power supply (-100v) 14 v nn negative high voltage power supply (-100v) 15 tx n output of the high voltage n-dmos drain (open drain output) 16 tx n output of the high voltage n-dmos drain (open drain output) 17 nc no connection 18 tx p output of the high voltage p-dmos drain (open drain output) 19 tx p output of the high voltage p-dmos drain (open drain output) 20 v pp positive high voltage power supply (+100v) 21 v pp positive high voltage power supply (+100v) 22 v pp positive high voltage power supply (+100v) 23 v pp positive high voltage power supply (+100v) 24 v pp positive high voltage power supply (+100v) 25 pgate gate input of the high voltage p-dmos, 10nf external cap from pin 31 (p dr ) 26 out p damp p-dmos drain (open drain output) 27 rgnd p ground return of damp p-dmos 28 v sub substrate connection of control / driver die chip (connected to the most positive supply, v p p) 29 v dd positive voltage supply for drive circuitry (+12v) 30 v dd positive voltage supply for drive circuitry (+12v) 31 p dr output of low voltage drive buffer for p-dmos, 10nf external cap to pin 25 (pgate) 32 gnd drive power ground 33 gnd drive power ground 34 dmpi connects to damp power p-dmos gate, 10nf cap to pin 1 (dmpo) 35 p in input logic control of the high voltage p-dmos pin 18 &19 (tx p) , hi = on, low = off 36 v ln negative low voltage power supply (C5v) 37 av dd positive analog voltage power supply (+12v) 38 agnd analog signal ground (0v) 39 v sub substrate connection of control / driver chip (connected to the most positive supply) 40 en control / drive chip power enable hi = on, low = off 41 damp input of damp control on both pin 26 (out p ) and pin 8 (out n ), hi = on, low = off 42 clamp input of clamp switches on both gates of output p-dmos and n-dmos, hi = on, low = off 43 v ll positive voltage supply of low voltage logic (+1.8v to +5v) 44 n in input logic control of the high voltage n-dmos pin 15 & 16 (tx n ), hi = on, low = off note: the three thermal slabs on the bottom of the package must be externally connected pad1 to v sub , pad2 to tx n , and pad3 to tx p .
supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 222-8888 / fax: (408) 222-4895 www.supertex.com ?2006 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell its products for use in s uch applications, unless it receives an adequate "product liability indemnification insurance agreement". supertex does not assume responsibility for use of devices described and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and spe cifications are subject to change without notice. for the latest product specifications, refer to the supertex website: http//www.supertex.com. 10 doc.# dsfp - HV732 nr040506 HV732 44-lead qfn (k6) package outline (the package drawing(s) in this data sheet may not re? ect the most current speci? cations. for the latest package outline information go to http://www.supertex.com/packaging.html .) 1 44 1.77 [.070] 1.57 [.062]typ 0.36 [.014] 0.26 [.010] 1.77 [.070] 1.57 [.062]typ 0.53 [.021] 0.48 [.019] 0.28 [.011] 0.23 [.009] 0.45 [.018] 0.35 [.014] 0.38 [.015] 0.28 [.011] 0.51 [.020] 0.41 [.016] 3.35 [.141] 3.37 [.133] 4.40 [.173] 4.20 [.165] 0.74 [.029] 0.69 [.027] 7.13 [.281] 6.87 [.271] 7.13 [.281] 6.87 [.271] pad2 pad3 11 12 22 note: 1. dimensions in mm. [inch] 2. radius is 0.127mm 3. three thermal slabs on the bottom of the package must be externally connected pad1 to v sub , pad2 to tx n , and pad3 to tx p . 0.05 [.002] 0.00 [.000] 1.00 [.039] 0.85 [.033] (n) (p) top view pad1
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